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TORRENT DETAILS
Udemy - Verilog HDL Programming With Practical Approach
TORRENT SUMMARY
Status:
All the torrents in this section have been verified by our verification system
Language: English | Size: 2.82 GB | Duration: 6h 47m
Fundamentals, levels of design description, Datatypes, test benchs, Tasks & system tasks, FSM with examples & Projects
What you'll learn
Learning Verilog HDL Programming fundamental concepts and properties compare to C Language, feature & advantages of Verilog HDL over VHDL
VLSI Design flow ( FPGA & ASIC) and Difference between FPGA vs ASIC
Different design methodologies in Verilog HDL programming with examples
Behavioral modeling with blocking & Non-Blocking concepts and real time examples
Test bench Verilog program with examples
Task & system tasks with examples for random data generator, file based operations and memory load operations, and file representation input & output etc.
Finite state machine (FSM) with example for both Mealy & Moore and Sequence detector FSM
Complete design & test bench programming for Memory controllers
Complete design & test bench programming for FIFO controller
Complete design & test bench programming for Encoder & decoder for Hamming code Error detection correction
Basics of FPGA
Requirements
Intension to learn
basic in C Language
basics in Digital design ( not compulsory)
Description
Complete Verilog HDL programming course with a perfect, well structured and concise course for freshers and experienced, as it is from fundamental level to the application level. This course discuss the concepts in Verilog HDL programming and properties compared with C-Language and discussing the features and advantages.
In this course we give information related to VLSI design flow for FPGA & ASIC and gives overview about both.
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FILE LIST
Filename
Size
~Get Your Files Here !/01 - Introduction to the course/001 Preview.mp4
84.6 MB
~Get Your Files Here !/01 - Introduction to the course/001 Preview_en.vtt
15 KB
~Get Your Files Here !/01 - Introduction to the course/002 Sample program on edaplayground.mp4
87.8 MB
~Get Your Files Here !/01 - Introduction to the course/002 Sample program on edaplayground_en.vtt
13.1 KB
~Get Your Files Here !/02 - Introduction to Verilog HDL/001 Verilog fundamentals.mp4
165.6 MB
~Get Your Files Here !/02 - Introduction to Verilog HDL/001 Verilog fundamentals_en.vtt
30 KB
~Get Your Files Here !/03 - VLSI design flow ( FPGA & ASIC)/001 VLSI Design flow (FPGA & ASIC).mp4
76.5 MB
~Get Your Files Here !/03 - VLSI design flow ( FPGA & ASIC)/001 VLSI Design flow (FPGA & ASIC)_en.vtt
14.3 KB
~Get Your Files Here !/03 - VLSI design flow ( FPGA & ASIC)/002 FPGA vs ASIC.mp4
80.1 MB
~Get Your Files Here !/03 - VLSI design flow ( FPGA & ASIC)/002 FPGA vs ASIC_en.vtt
8.7 KB
~Get Your Files Here !/04 - Three levels of verilog design Description/001 Three levels of verilog design Description.mp4
32.9 MB
~Get Your Files Here !/04 - Three levels of verilog design Description/001 Three levels of verilog design Description_en.vtt
3.7 KB
~Get Your Files Here !/04 - Three levels of verilog design Description/002 Example mux_2x1 with 3 abstracts models.mp4
9.1 MB
~Get Your Files Here !/04 - Three levels of verilog design Description/002 Example mux_2x1 with 3 abstracts models_en.vtt
1.8 KB
~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/001 Language constructs -Comments, keywords, identifier, Number specific, Operators.mp4
14.5 MB
~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/001 Language constructs -Comments, keywords, identifier, Number specific, Operators_en.vtt
2.2 KB
~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/002 Datatypes - net,reg, integer, real, string, time, Parameter, Vector,Array,Memory.mp4
17.8 MB
~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/002 Datatypes - net,reg, integer, real, string, time, Parameter, Vector,Array,Memory_en.vtt
3 KB
~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/003 Compiler Directives.mp4
15.9 MB
~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/003 Compiler Directives_en.vtt
2 KB
~Get Your Files Here !/06 - Verilog Program structure/001 Verilog Program Structure -Module.mp4
7.4 MB
~Get Your Files Here !/06 - Verilog Program structure/001 Verilog Program Structure -Module_en.vtt
1.1 KB
~Get Your Files Here !/06 - Verilog Program structure/002 Ports.mp4
10.7 MB
~Get Your Files Here !/06 - Verilog Program structure/002 Ports_en.vtt
1.8 KB
~Get Your Files Here !/06 - Verilog Program structure/003 Port Connection Rules.mp4
13 MB
~Get Your Files Here !/06 - Verilog Program structure/003 Port Connection Rules_en.vtt
1.9 KB
~Get Your Files Here !/06 - Verilog Program structure/004 Design Methodologies Approaches.mp4
4.7 MB
~Get Your Files Here !/06 - Verilog Program structure/004 Design Methodologies Approaches_en.vtt
849 B
~Get Your Files Here !/07 - Gate level modeling/001 Gate Level Model Introduction.mp4
3.4 MB
~Get Your Files Here !/07 - Gate level modeling/001 Gate Level Model Introduction_en.vtt
655 B
~Get Your Files Here !/07 - Gate level modeling/002 Example 4x1 Mux.mp4
5.4 MB
~Get Your Files Here !/07 - Gate level modeling/002 Example 4x1 Mux_en.vtt
932 B
~Get Your Files Here !/07 - Gate level modeling/003 Example Full Adder.mp4
3.6 MB
~Get Your Files Here !/07 - Gate level modeling/003 Example Full Adder_en.vtt
733 B
~Get Your Files Here !/07 - Gate level modeling/004 Tri-state Buffers with Examples.mp4
12.9 MB
~Get Your Files Here !/07 - Gate level modeling/004 Tri-state Buffers with Examples_en.vtt
2 KB
~Get Your Files Here !/07 - Gate level modeling/005 Array of Instance with example.mp4
10.7 MB
~Get Your Files Here !/07 - Gate level modeling/005 Array of Instance with example_en.vtt
1.6 KB
~Get Your Files Here !/08 - Data flow modeling/001 Data flow Modeling assign statement.mp4
12.9 MB
~Get Your Files Here !/08 - Data flow modeling/001 Data flow Modeling assign statement_en.vtt
2.3 KB
~Get Your Files Here !/08 - Data flow modeling/002 Operators.mp4
17.2 MB
~Get Your Files Here !/08 - Data flow modeling/002 Operators_en.vtt
1.9 KB
~Get Your Files Here !/08 - Data flow modeling/003 Arithmetic Operators.mp4
8.5 MB
~Get Your Files Here !/08 - Data flow modeling/003 Arithmetic Operators_en.vtt
1.4 KB
~Get Your Files Here !/08 - Data flow modeling/004 Logical Operators.mp4
12.7 MB
~Get Your Files Here !/08 - Data flow modeling/004 Logical Operators_en.vtt
1.6 KB
~Get Your Files Here !/08 - Data flow modeling/005 Example Full Adder Logical operators.mp4
3.8 MB
~Get Your Files Here !/08 - Data flow modeling/005 Example Full Adder Logical operators_en.vtt
811 B
~Get Your Files Here !/08 - Data flow modeling/006 Example Full Adder Arithmetic operators.mp4
2.8 MB
~Get Your Files Here !/08 - Data flow modeling/006 Example Full Adder Arithmetic operators_en.vtt
776 B
~Get Your Files Here !/08 - Data flow modeling/007 Example Binary to Gray code converter.mp4
4.6 MB
~Get Your Files Here !/08 - Data flow modeling/007 Example Binary to Gray code converter_en.vtt
891 B
~Get Your Files Here !/08 - Data flow modeling/008 Logical and , Logical or (&&, ).mp4
5.6 MB
~Get Your Files Here !/08 - Data flow modeling/008 Logical and , Logical or (&&, )_en.vtt
1.4 KB
~Get Your Files Here !/08 - Data flow modeling/009 Shift operators Leftright Shift.mp4
17.9 MB
~Get Your Files Here !/08 - Data flow modeling/009 Shift operators Leftright Shift_en.vtt
2.3 KB
~Get Your Files Here !/08 - Data flow modeling/010 Shifting without shift operator , just with concatenation operator.mp4
4.3 MB
~Get Your Files Here !/08 - Data flow modeling/010 Shifting without shift operator , just with concatenation operator_en.vtt
1.3 KB
~Get Your Files Here !/08 - Data flow modeling/011 Ternary operator Example 2x1 MUX, 4x1 MUX.mp4
13.6 MB
~Get Your Files Here !/08 - Data flow modeling/011 Ternary operator Example 2x1 MUX, 4x1 MUX_en.vtt
3.2 KB
~Get Your Files Here !/08 - Data flow modeling/012 Relational operators Example Comparator.mp4
4.5 MB
~Get Your Files Here !/08 - Data flow modeling/012 Relational operators Example Comparator_en.vtt
854 B
~Get Your Files Here !/08 - Data flow modeling/013 Equality (==) , case Equality (===) operators.mp4
7.1 MB
~Get Your Files Here !/08 - Data flow modeling/013 Equality (==) , case Equality (===) operators_en.vtt
1.9 KB
~Get Your Files Here !/08 - Data flow modeling/014 Reduction operator Example Parity Generator.mp4
7.1 MB
~Get Your Files Here !/08 - Data flow modeling/014 Reduction operator Example Parity Generator_en.vtt
1.3 KB
~Get Your Files Here !/08 - Data flow modeling/38061230-arthm1.mp4
3.8 MB
~Get Your Files Here !/09 - Behavioral Modeling/001 Behavioral Modeling - Introduction.mp4
67 MB
~Get Your Files Here !/09 - Behavioral Modeling/001 Behavioral Modeling - Introduction_en.vtt
7.8 KB
~Get Your Files Here !/09 - Behavioral Modeling/002 Behavioral Modeling Constructs.mp4
15.4 MB
~Get Your Files Here !/09 - Behavioral Modeling/002 Behavioral Modeling Constructs_en.vtt
1.8 KB
~Get Your Files Here !/09 - Behavioral Modeling/003 Procedural Blocks- initial & always.mp4
61.1 MB
~Get Your Files Here !/09 - Behavioral Modeling/003 Procedural Blocks- initial & always_en.vtt
7.6 KB
~Get Your Files Here !/09 - Behavioral Modeling/004 Example Clock Generation.mp4
8.4 MB
~Get Your Files Here !/09 - Behavioral Modeling/004 Example Clock Generation_en.vtt
2.1 KB
~Get Your Files Here !/09 - Behavioral Modeling/005 Assignment Statements - Blocking & Non-blocking.mp4
63.3 MB
~Get Your Files Here !/09 - Behavioral Modeling/005 Assignment Statements - Blocking & Non-blocking_en.vtt
7 KB
~Get Your Files Here !/09 - Behavioral Modeling/006 Mechanism in Non-blocking.mp4
4.4 MB
~Get Your Files Here !/09 - Behavioral Modeling/006 Mechanism in Non-blocking_en.vtt
1.2 KB
~Get Your Files Here !/09 - Behavioral Modeling/007 Concurrency.mp4
6.4 MB
~Get Your Files Here !/09 - Behavioral Modeling/007 Concurrency_en.vtt
1.2 KB
~Get Your Files Here !/09 - Behavioral Modeling/008 Advantage of Non-blocking assignment Example swapping.mp4
10.2 MB
~Get Your Files Here !/09 - Behavioral Modeling/008 Advantage of Non-blocking assignment Example swapping_en.vtt
1.4 KB
~Get Your Files Here !/09 - Behavioral Modeling/009 Advantage of Non-blocking assignment Example Pipelining.mp4
38.4 MB
~Get Your Files Here !/09 - Behavioral Modeling/009 Advantage of Non-blocking assignment Example Pipelining_en.vtt
5.6 KB
~Get Your Files Here !/09 - Behavioral Modeling/010 if-else statement Example 4x1 Mux.mp4
30.4 MB
~Get Your Files Here !/09 - Behavioral Modeling/010 if-else statement Example 4x1 Mux_en.vtt
4.3 KB
~Get Your Files Here !/09 - Behavioral Modeling/011 Case – statement Example 4x1 Mux.mp4
34.1 MB
~Get Your Files Here !/09 - Behavioral Modeling/011 Case – statement Example 4x1 Mux_en.vtt
3.6 KB
~Get Your Files Here !/09 - Behavioral Modeling/012 Advantage of Case over if-else.mp4
8 MB
~Get Your Files Here !/09 - Behavioral Modeling/012 Advantage of Case over if-else_en.vtt
1 KB
~Get Your Files Here !/09 - Behavioral Modeling/013 Loops while, for, repeat, forever.mp4
7.2 MB
~Get Your Files Here !/09 - Behavioral Modeling/013 Loops while, for, repeat, forever_en.vtt
1.4 KB
~Get Your Files Here !/09 - Behavioral Modeling/014 Parallel blocks - fork-join.mp4
10.8 MB
~Get Your Files Here !/09 - Behavioral Modeling/014 Parallel blocks - fork-join_en.vtt
1.7 KB
~Get Your Files Here !/09 - Behavioral Modeling/015 Combinational Logic Circuit Examples 8x1 Mux.mp4
7.6 MB
~Get Your Files Here !/09 - Behavioral Modeling/015 Combinational Logic Circuit Examples 8x1 Mux_en.vtt
1.8 KB
~Get Your Files Here !/09 - Behavioral Modeling/016 Example 8x1 Mux using 4x1 mux and 2x1 mux.mp4
